In data processing systems which require the transfer of blocks of data between input/output (I/O) devices and the main memory of the system, such data normally is transferred via an appropriate bus, usually termed the I/O data bus, and requires the central processor unit (CPU) of the system to suspend its operation so as to make available appropriate registers internal to the processor for use in the data transfer operation. Moreover, the processor's own internal memory control signals are required to control the transfer to and from the memory via the central processor unit. For each data word which makes up the block of data words which are to be transferred, the processor controller is required to transfer an address from the I/O device, for example, to the processor, the address being then either directly used as a physical address to access the memory or appropriately supplied to a memory allocation and protection (MAP) unit of the processor which translates the logical address supplied by the input logic into the physical address for accessing the main memory into which or from which the data is to be transferred. The processor must also then handle the actual data word in its registers for appropriate transfer either into the memory or from the memory via the data processing system's memory bus. For each data word which is to be transferred, one address and one data word must be handled by the central processor unit. The handling of the address in the CPU registers and the MAP unit normally takes a reasonably long time period and the overall transfer cycle time can be as high as 1.5 to 2 microseconds in some systems. During such time period the central processor unit cannot perform any other operations which require the registers which are being so used and, therefore, the efficiency of its use is low. In such standard data channel transfer operations, the I/O devices may be sufficiently slow in their operation that the use of anything other than a standard low-speed data channel provides no real advantage. However, when dealing with high speed I/O devices it is desirable to avoid the unnecessarily long time period for address and data processing so that suspension of the CPU operation is minimized.